The present invention pertains to the field of videophone system applied to narrow band digital network, and more particularly relates to videophone system for enhancing its performance by using DSP (Digital Signal Processor) in image coder and decoder (hereinafter referred to as "codec").
The image compression code techniques in videophone service of narrow band digital natwork were required and could be performed by processing real-time image. The conventional hardware systems regarding this field are classified into the following two architectures. One is to implement image data compression algorithms by general integrated circuit. The other is to implement them by several DSP chips and digital processing software. The former has a disadvantage that the hardware design for forming the coding algorithms is very complicated. The latter has a disadvantage that the efficiency is lowered due to bus contention and dependence on DSP chip performance. An example of the latter system is hereinafter described with reference to FIG. 1. The videophone system of FIG. 1 was provided by AEG RESEARCH located in West Germany. In FIG. 1, reference number 10 shows CPU 68020, 11 VME (Versa Module Europe) bus, 12 1M Byte Frame memory, 13 ADSP (Analog Digital Signal Processor), 14 DRAM (Dynamic Random Access Memory), 15 memory bus, 16 video bus, 17 A/D converter, and 18 D/A converter, respectively.
ADSP's contain the DRAM(14), respectively. ADSP's 13 are coupled to each other and also to frame memory 12 via the memory bus 15. ADSP's 13 communicate with CPU 10 via VME bus 11. As seen above well, the above system's efficiency was lowered due to bus contention caused by all ADSP's 13 using the VME bus 11 and the memory bus 15.